Synopsys joins hands with TSMC to launch first A14 process design kit at the end of the year

Synopsys, an American electronic design automation company, announced on the 18th that it has cooperated with TSMC to develop a design process for TSMC’s A14 process, and is expected to launch the first set of process design kits by the end of 2025.

Synopsys issued a press release stating that Synopsys.ai, its analog and digital processes as well as its AI capabilities, has passed TSMC's N2P and A16 process certification based on the NanoFlex architecture, which can help optimize performance and power consumption, and expand chip design to advanced semiconductor technologies.

Synopsys pointed out that the certified features for TSMC’s A16 Super Power Rail (SPR) process design can effectively improve power distribution and system performance while maintaining the thermal stability of the die back-winding design.

Synopsys stated that the pin connection method based on pattern architecture has been enhanced for TSMC's A16 process to provide competitive area results. The two parties have also begun to develop a design process for TSMC's AI process, and are expected to launch the first set of process design kits by the end of 2025.

TSMC pointed out that it maintains close cooperation with long-term partners in the open innovation platform (OIP) ecosystem, including Synopsys, to assist customers in system-on-chip (SoC) design to achieve high quality and faster product launch time.

TSMC stated that as the market demand for energy-saving and high-performance AI chips continues to grow, the collaboration of the OIP ecosystem is crucial to providing mutual customers with certified electronic design automation (EDA) tools, design processes, and high-quality IP to ensure that they can meet or exceed their design goals.

Synopsys pointed out that it continues to work closely with TSMC to provide multi-die solutions, covering advanced EDA and IP products, which can support TSMC's cutting-edge process and packaging technology to drive innovation in AI chips and multi-die designs.

Synopsys stated that its 3DIC Compiler, which is tuned for 3D packaging, has discovered a sign-off platform and IP and has achieved the rollout of multiple customer chip designs.